1. Field of the Invention
This invention relates to the manufacture of electronic modules, namely flip chip packaging, utilizing an improved method of assembling the module. The improved method allows for enhanced contact with less stressing on the solder joints used to electrically interconnect a chip and a substrate resulting in an electronic module having higher integrity and reliability.
2. Description of Related Art
Multi-layer ceramic electronic components are typically joined together by soldering pads on a surface of one of the electronic components to corresponding pads on the surface of the other component. Controlled Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wire bonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multi-layer ceramic substrate and pads on the chip are electrically and mechanically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10.times.10 array on the multi-layer ceramic surface.
One of the key features in using flip chip packaging is the ability to accommodate a considerable distortion in pattern between the chip and the substrate. This accommodation is due to a self-alignment capability produced by surface tension minimization of the solder joints. What cannot be tolerated, however, is any significant deviation from planarity between the chip surface and the substrate surface since electrical interconnection cannot occur unless the solder bump on the chip physically contacts the substrate.
Multi-layer ceramic (MLC) chip carriers with flip chip technology often possess, due to design, the tendency to have localized bulges at the location of underlying substrate vias. In addition, residual camber (non-planarity) from sintering the substrate can lead to further non-planarity across the chip site. A camber magnitude much greater than about 25 to 30 microns will lead to non-contact opens after a chip join attempt. Thus, it is desirable to find a way of overcoming the non-planarity typically found on a chip and substrate used in flip chip packaging resulting in better solder interconnections.
U.S. Pat. No. 5,587,337 to Idaka et al. discloses a method of manufacturing bump electrodes with a larger top surface area than bottom surface area. Both surfaces are flat which would not overcome the non-planarity of a chip and substrate when joining such components in flip chip packaging.
U.S. Pat. No. 5,527,734 to van der Putten discloses a method of forming solder interconnections having a truncated pyramid shape. The truncated pyramidal shape of the solder is formed using an electroless metallization bath. This reference neither suggests nor discloses a method of overcoming the non-planarity of components in flip chip packaging. The flat top surface of the solder would not overcome the non-planarity of the electronic components in an electronic module.
U.S. Pat. No. 5,478,007 to Marrs discloses a method and structure for flip chip interconnection of a chip to a substrate utilizing a ball bond having a conical section and a base section. The disclosure includes a number of additional steps in forming the ball bond which add to an already cumbersome process. The reference neither suggests nor discloses a method of overcoming the non-planarity of the electronic components in a module.
U.S. Pat. No. 5,244,143 to Ference et al. (and assigned to the assignee of the present invention) discloses an apparatus and method of injection molding solder mounds onto electronic devices. This reference neither suggests nor disclose a method of overcoming the non-planarity of the electronic components when assembling electronic modules.
U.S. Pat. No. 4,751,563 to Laibowitz et al. discloses an interconnect with a contamination resist cone formed on a substrate. This reference neither suggests nor discloses a method or apparatus for overcoming the non-planarity of electronic components when assembling electronic modules.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of overcoming the non-planarity of electronic components used in assembling electronic modules.
It is another object of the present invention to provide a method of assembling electronic modules having improved solder interconnections.
It is yet another object of the present invention to provide a solder preform which overcomes the problem of camber on electronic components used in flip chip packaging.
A further object of the invention is to provide an electronic module having improved reliability, integrity and less prone to electrical failure of solder interconnections.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.